From Singapore: Independent researcher Claudio Lorenzo La Rosa recently published 5500FP: A 24-Trit Balanced Ternary RISC Processor, marking a quiet but significant milestone in hardware architecture. The 5500FP is a ternary CPU implemented on an FPGA, and while it is not very fast, it makes it easier to experiment with computers that do not use binary. This is the first generally available, off-the-shelf ternary processor since the 1960s, opening a window on a computing path the industry abandoned decades ago.
The case for ternary is mathematically straightforward. Ternary computing involves using trits with three states instead of bits with two. In balanced ternary, those three states are represented as minus-one, zero, and plus-one. One trit can hold approximately 1.58x more data than one bit. This density advantage has appealed to computing theorists for generations. Donald Knuth called it "perhaps the prettiest number system", and Setun, built in 1958 in the Soviet Union at Moscow State University, had notable advantages over the binary computers that eventually replaced it, such as lower electricity consumption and lower production cost.
Why did ternary fade? Setun was discontinued not because it failed but because "the world" had already chosen a technological standard based on economic and industrial inertia; the capitalist world settled on binary computing because it was simpler to manufacture and already entrenched in corporate and military infrastructures, and once that happened, there was no going back. By the 1970s, binary had become a self-reinforcing standard. Chips were optimised for binary. Software assumed binary. Engineering tools were designed for binary. Switching costs made alternatives economically unviable.
But the ternary question has resurged. Ternary computing shows promise for implementing fast ternary large language models and potentially other AI applications, in lieu of floating point arithmetic. In AI, we are struggling with how to efficiently simulate multi-state neurons on a binary system; in quantum computing, we are moving toward qutrits, which functionally resemble balanced ternary computing.
La Rosa's implementation reveals both the promise and the practical constraints. The 5500FP is a 24-trit balanced ternary RISC processor implemented on FPGA, with a 120-instruction ISA, native atomic synchronisation primitives, and an open hardware development board, demonstrating the practical feasibility of balanced ternary computing on modern reconfigurable hardware. However, the device is simulating ternary logic with binary logic, meaning each trit is represented as two bits, and these are then converted via analogue circuitry into balanced ternary for the external bus interface. This two-bits-per-trit compromise reduces the storage advantage but ensures compatibility with existing binary-based electronics.
The real barriers to ternary adoption remain technological and economic rather than theoretical. Much of the improved efficiency in interconnection and digit representation is balanced by requiring more gates in computations; ternary addition, while achieving the same computational speed as binary addition, requires 62 per cent more logic. Decades of optimisation have made binary circuits far more efficient in practice than ternary alternatives. For three-valued or ternary computing to be an alternative for binary, new multiple valued logic electronic design automation tools are needed.
La Rosa's work signals renewed interest in the question: what computing paradigm might we have built if binary had not become the standard? The 5500FP is not fast or practical for commercial use. But it proves the concept works, and it provides researchers with a testbed for exploring whether ternary can claim space in an age of AI acceleration and quantum information processing. Whether it becomes more than a curiosity depends on whether funding and engineering effort can overcome six decades of binary momentum.