IBM and Lam Research have announced a five-year collaboration aimed at developing new processes and materials to support sub-1nm logic scaling, building on a long record of successful partnerships that will focus on the joint development of novel materials, fabrication processes, and High-NA EUV lithography processes.
The partnership deepens a decade-long technical relationship and marks a significant bet on the future direction of semiconductor manufacturing. The work will take place at IBM Research's facilities at the NY Creates Albany NanoTech Complex in Albany, New York.
Using IBM's advanced research capabilities at the NY Creates Albany NanoTech Complex and Lam's end-to-end process tools and innovations, including Aether dry resist technology, Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and advanced packaging technologies, the teams will build and validate full process flows for nanosheet and nanostack devices and backside power delivery. Together, these capabilities are aimed at allowing High-NA EUV patterns to be reliably transferred into real device layers with high yield and enabling continued scaling, improved performance, and viable paths to production for future logic devices.
Semiconductors have grown ever smaller for decades, following Moore's Law and enabling faster, more efficient computing. But manufacturers are running into fundamental challenges at these extreme scales. Standard EUV lithography utilises chemically amplified resists, which are spin-coated onto wafers and developed using wet chemistry, but that approach has a fundamental problem at the geometries high-NA EUV scanners are designed to print: stochastic noise, which is a statistical variation in photon absorption per unit area that drives defect rates up as features shrink.
Aether's process sidesteps wet chemistry entirely by depositing the resist via vapour-phase precursors and developing it using plasma-based dry processes, with its metal-organic compounds absorbing three to five times more EUV light than conventional carbon-based resist materials, reducing the exposure dose required per wafer pass and keeping single-print patterning viable at nodes where wet-process alternatives would require more expensive multi-patterning.
The technical innovation addresses a real bottleneck. Fewer process steps between exposure and etch reduce the number of points at which pattern fidelity can degrade, which is a compounding advantage as geometries continue to tighten. At sub-1nm scales, even tiny imperfections cascade into manufacturing failures.
Nanosheet transistors, which stack multiple thin sheets of silicon to increase drive current without widening the transistor footprint, are one of the primary device architectures the teams will be validating. This approach is part of a broader shift from making transistors smaller to making them more efficient through three-dimensional design.
The two companies have worked together for more than a decade, contributing to 7nm process development, nanosheet transistor architecture, and early EUV process integration, with IBM unveiling what it described as the world's first 2nm node chip in 2021 as part of that ongoing partnership. The new agreement extends that track record.
The collaboration matters beyond IBM and Lam. This follows the same model as the companies' prior work on 7nm and nanosheet, with the research demonstrated at Albany eventually feeding into production processes at TSMC and others, with sub-1nm process work starting in 2026 therefore unlikely to reach volume manufacturing before the early 2030s.
The collaboration also presents a huge opportunity for Lam. If it's able to establish Aether as the validated dry resist solution for high-NA EUV logic, it stands to add a significant new revenue category on top of the etch and deposition tools it already sells to nearly every advanced chipmaker, and a five-year commitment with IBM builds process familiarity and customer confidence well before foundries are making resist process decisions for their sub-1nm nodes.
The investment reflects the high stakes. New York State announced a partnership with IBM, Micron, and other industry players to invest $10 billion into expanding the Albany NanoTech Complex with a new cutting-edge High NA EUV Center that will drive the next decade of semiconductor technology innovations. Albany has become central to maintaining American and Western leadership in semiconductor research at the most advanced nodes.
At a broader level, this partnership demonstrates how semiconductor scaling now requires deep collaboration between equipment makers, materials researchers, and foundries. No single company can push the boundaries alone. As transistor dimensions approach the scale of atoms themselves, the problems become less about incremental improvement and more about fundamental physics and materials science.