IBM and Lam Research have announced a five-year collaboration aimed at overcoming one of semiconductor manufacturing's toughest remaining challenges: pushing logic chip scaling beyond 1 nanometre.
The partnership will develop the materials and fabrication processes needed to scale logic chips beyond 1nm using High NA EUV lithography and Lam's Aether dry resist technology. The work will take place at IBM Research's facilities at the NY Creates Albany NanoTech Complex in Albany, New York.
The announcement represents a significant escalation of a relationship that has already delivered major breakthroughs. The two companies have worked together for more than a decade, contributing to 7nm process development, nanosheet transistor architecture, and early EUV process integration, with IBM unveiling what it described as the world's first 2nm node chip in 2021 as part of that ongoing partnership.
The new five-year agreement targets a series of engineering obstacles that have proven formidable. Lam's Aether dry resist technology has an edge over conventional wet processes because fewer steps between exposure and etch mean less opportunity for pattern degradation at tighter geometries. This matters enormously: as transistors shrink, even microscopic imperfections compound manufacturing problems. Aether's metal-organic compounds absorb three to five times more EUV light than traditional carbon-based resist materials, which reduces the exposure dose needed per wafer pass and helps maintain single-print patterning at advanced nodes without resorting to more expensive multi-patterning.
High NA EUV itself represents a generational leap in lithography capability. Numerical aperture (NA) is the measure of how finely a lithography system can focus light; the NA for High NA EUV lithography is 0.55, which is considerably larger than the previous EUV generation's 0.33. High-NA EUV systems utilize optics with a numerical aperture of 0.55 rather than 0.33, achieving minimum feature sizes of 8nm versus 13nm. This enhanced resolution is essential for stamping transistors at dimensions approaching the atomic scale.
Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery, using Lam's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist. These technologies address practical manufacturing constraints: enabling transistors to stack vertically, routing power through the wafer's rear surface, and transferring High NA EUV patterns into actual device layers without losing quality.
The partnership arrives at a pivotal moment for the semiconductor industry. Roadmaps for the deployment of high-NA EUV machinery published by leading foundries indicate plans for their installation starting in 2024-2025 to develop 2nm nodes, with deployment for volume manufacturing in 2026-2027. Major manufacturers including Samsung, SK Hynix, and Taiwan's TSMC are acquiring High NA EUV equipment and beginning pilot production. The race to reach sub-1nm scaling has become central to competitive advantage, especially as artificial intelligence workloads demand ever more powerful processing chips.
What remains unresolved are the technical trade-offs. High NA EUV systems are extraordinarily expensive; ASML's TWINSCAN EXE:5000 High-NA EUV system is priced at USD 370-400 million, compared to USD 200 million for their standard EUV systems. The cost-per-chip economics of sub-1nm manufacturing remain uncertain. Process maturity requires not just breakthrough materials and tooling but also years of validation work. The IBM-Lam agreement essentially commits both companies to solving these puzzles together, betting that the payoff in chip density and performance will justify the investment.