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Intel's Panther Lake die shots reveal ambitious 18A manufacturing strategy

High-resolution images expose detailed layout of Intel's first mobile processor built on its next-generation 2nm-class process node

Intel's Panther Lake die shots reveal ambitious 18A manufacturing strategy
Image: Toms Hardware
Key Points 2 min read
  • Annotated die shots reveal Panther Lake's compute tile, made on Intel's 18A process, houses 16 cores split into performance, efficiency, and low-power configurations
  • Intel's Xe3 graphics tile uses up to 12 cores on higher-end variants, manufactured on TSMC's N3E process to optimise cost and performance
  • The processor uses a modular tile design that separates CPU, GPU, and I/O functions, enabling Intel to create multiple product variants from fewer design components

Intel's recently revealed Core Ultra Series 3 Panther Lake-H die shot has now been annotated in greater detail, offering a much clearer look at how the company is structuring its next-generation mobile silicon.

At the centre of the design is the compute tile, the largest functional block, which is fabricated on Intel 18A, measures 14.32 mm by 8.04 mm for a total area of around 115 square millimetres. This tile houses the processor's full 16-core CPU configuration, made up of six Cougar Cove performance cores, eight Darkmont efficiency cores, and four additional low-power E-cores.

The compute tile also integrates more than just CPU execution resources. Intel has placed the primary memory controller there alongside an 8 MB memory-side cache, with support for dual-channel DDR5 and LPDDR5X memory up to 9600 MT/s. The tile also carries Intel's NPU 5, which includes three neural compute engines and a combined 4.5 MB of local scratchpad memory.

Graphics are split off into a dedicated tile based on the Xe3 Celestial architecture. Mainstream Panther Lake-H parts use a smaller 4 Xe-core graphics tile built on Intel 3, while the larger 12 Xe-core version intended for Panther Lake-U systems is built on TSMC N3E. This approach allows Intel to optimise manufacturing costs and performance characteristics for different market segments without redesigning the graphics architecture itself.

The I/O tile integrates the PCIe root complex, Thunderbolt 5 or USB4 V2 host router, four PCIe 5.0 lanes, eight PCIe 4.0 lanes, two Thunderbolt 5 ports, and integrated Wi-Fi 7 with Bluetooth 5.4.

The design continues Intel's disaggregated processor strategy, but Panther Lake-H appears to lean more heavily on the kind of tile partitioning previously seen with Lunar Lake. The result is a package that separates CPU, graphics, and I/O functions into dedicated silicon blocks while using a base tile and filler structures to complete the physical assembly.

Rather than introducing a fundamentally new CPU or GPU architecture, Panther Lake focuses on higher core counts, better graphics configurations, and increased power budgets enabled by a newer manufacturing node and modular tile-based design. Panther Lake has been widely praised for its power-efficiency and integrated graphics performance, having been noted as a "return to form" for Intel.

Intel has started volume production of its Core Ultra 3-series 'Panther Lake' processors, with the company designing the CPU to demonstrate Intel's ability to develop a competitive processor and produce it internally using its leading-edge manufacturing technology. The significance of these die shots lies not merely in visual detail but in what they reveal about Intel's strategic bet: a shift towards American-made semiconductor manufacturing that depends on the successful execution of advanced process technology, tighter system integration, and modular design principles that allow for product flexibility without excessive re-engineering.

Sources (3)
Sophia Vargas
Sophia Vargas

Sophia Vargas is an AI editorial persona created by The Daily Perspective. Covering US politics, Latin American affairs, and the global shifts emanating from the Western Hemisphere. As an AI persona, articles are generated using artificial intelligence with editorial quality controls.