From Dubai: The semiconductor industry runs on relentless efficiency gains, and most of them arrive at extraordinary cost. New EUV scanner generations from ASML carry price tags north of US$300 million. Advanced photoresist chemistry demands years of materials science investment. Against that backdrop, a discovery announced this week at the 2026 SPIE Advanced Lithography and Patterning Conference in San Jose stands out for its elegance: the Belgian research institute Imec has shown that simply increasing the oxygen concentration in a single baking chamber can lift photoresist performance by up to 20 per cent.
The step in question is the post-exposure bake, a critical heat treatment applied to silicon wafers after they have been exposed to extreme ultraviolet light but before the photoresist is chemically developed. It is a critical heat treatment step after EUV resist exposure and before resist development. In standard EUV production environments, wafers are exposed in a vacuum and then transferred to a bake module operating under normal cleanroom air containing 21 per cent oxygen. That atmospheric composition has, until now, been treated as an unalterable given.
Imec's researchers challenged that assumption directly. Scientists from Imec discovered that raising oxygen levels from 21 per cent to 50 per cent during the EUV post-exposure bake step results in a 15 to 20 per cent increase in photo-speed, which means the metal-oxide resist can reach its target dimension at a lower EUV dose. Senior researcher Ivan Pollentier put the finding plainly:
"We observe a 15–20% faster photo-speed when increasing the oxygen concentration from atmospheric 21% to 50% during post-exposure bake. The trend is observed for both model MOR and commercial MOR materials."
Faster photo-speed means the resist reaches target dimensions at a lower EUV dose, which directly improves EUV scanner throughput and reduces exposure cost. In practical terms, a fab running at the leading edge could process more wafers per hour from the same scanner without purchasing additional hardware. Lower dose cuts exposure time, which in turn increases an EUV scanner's throughput per hour and can reduce the cost of the EUV step per wafer and ultimately per chip, though do not expect the lowered exposure cost to have a significant impact on the cost of the final product. That last caveat is worth holding onto: chipmaking cost is spread across hundreds of process steps, and no single improvement transforms the economics overnight.
To isolate and study the oxygen effect, Imec built a purpose-designed research platform. The results were achieved using BEFORCE, a unique research tool developed by Imec to investigate the role of the ambient environment on critical dimension stability and performance of metal-oxide resists. In commercial EUV clusters, resist-coated wafers are exposed in vacuum and then transferred to the post-exposure bake unit, where they are heated under atmospheric conditions. The BEFORCE tool mimics these operations, but the wafer transfer and post-exposure bake are isolated from the cleanroom atmosphere and can be performed in precisely controlled environments through gas injection and mixing systems. The full name of the tool reveals its scope: Bake and EUV system with FTIR and Outgas measurement for Resist Evaluation in Controlled Environment.
Gas composition in the PEB chamber has not been widely treated as an EUV optimisation variable, which makes the announcement significant, but it remains to be seen whether this can be industrialised. That caveat about industrialisation is the central tension in the story. To put Imec's discovery into use, foundries will have to ask their fab tool makers to replicate what BEFORCE does during the PEB step. That is not a trivial engineering challenge. The post-exposure bake is, by the standards of the lithography flow, one of its most sensitive operations; controlling temperature, ramp rate, bake duration, and now gas composition simultaneously, at volume and repeatability, demands that equipment manufacturers redesign their bake modules from first principles.
The resists themselves are worth understanding. Metal-oxide resists have emerged as leading candidates for advanced EUV lithography applications, offering superior resolution, reduced line-edge roughness, and good EUV dose-to-size performance compared to chemically amplified resists. Their better pattern transfer capability for small features and thin resist films makes them particularly attractive for the highest resolution metal layers, exposed using High-NA EUV lithography. High-NA EUV, the next generation of lithography tools from ASML, is widely expected to begin appearing in high-volume manufacturing over the coming years, making research that optimises metal-oxide resist performance timely rather than speculative.
There is a legitimate scientific question still to answer. To optimally exploit the positive impact of gas compositions on MOR performance, a more fundamental understanding of the chemical mechanism at play during the resist's post-exposure bake is essential. Experiments are ongoing to correlate MOR performance to observations of chemical changes during bake, captured by an integrated Fourier transform infrared spectrometer, under varying environmental conditions. In other words, Imec knows that oxygen helps; it does not yet have a complete account of why. That is not unusual in semiconductor research, where empirical findings frequently precede mechanistic explanation, but it does mean the optimisation curve could look quite different once the chemistry is fully understood.
For those watching from Canberra or from Australia's nascent semiconductor sector, this kind of research matters at a remove but a meaningful one. Australia's notable lack of participation in the global semiconductor ecosystem has put it at a geopolitical disadvantage. As a nation, with some niche exceptions, it is almost entirely dependent on foreign-controlled microchip technology, making it increasingly vulnerable to global supply-chain shortages, shutdowns and disruptions. The Australian Strategic Policy Institute has argued for years that sovereign semiconductor capability is not merely an economic aspiration but a national security requirement, particularly given Australia's commitments under AUKUS. The advanced technologies identified as critical under AUKUS are all dependent on semiconductors and therefore should explicitly consider how this enabling technology can be secured to begin with.
Australia is spending public money on the foundations. In October 2023, the Australian National Fabrication Facility received AUD 47.4 million under the National Collaborative Research Infrastructure Strategy to support semiconductor device R&D. Further backing came in February 2024, with over AUD 51 million allocated through the Cooperative Research Centers Projects programme for twenty-one R&D projects across compound semiconductors, advanced packaging, and quantum devices. Those are meaningful sums for a country starting largely from scratch in chip fabrication, but they are modest relative to the capital commitments being made in the United States, Europe, Japan, and South Korea. The gap between research investment and commercial-scale manufacturing capability remains wide.
The honest assessment of Imec's oxygen finding sits somewhere between transformative and incremental. The underlying insight, that a variable no one was actively managing turns out to matter considerably, is genuinely significant. This marks the first evidence that performing post-exposure lithography steps under controlled ambient environments can reduce EUV exposure dose, delivering a new pathway to higher EUV lithography throughput. Equipment makers now have a concrete design target. Foundries have a commercial incentive to demand it. The research path toward understanding the mechanism is defined. What remains open is the timeline and cost of engineering the discovery into production tools at the scale of TSMC, Samsung, or Intel. That path typically takes years, and occasionally dead-ends entirely when laboratory conditions resist translation to a fab floor running millions of wafers a year.
What the finding does confirm is that there are still unobvious optimisation levers in a process most assumed had been exhaustively characterised. For an industry where squeezing another few percentage points of throughput from existing hardware can be worth billions of dollars annually, that is a discovery worth taking seriously, even before the chemistry is fully explained and the engineering is proven at scale. The Australian National Fabrication Facility and the research community it supports would do well to track what comes next from Leuven.